Biggest pet peeve of FPGA toolchains
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I’m interested - what’s everyone’s most hated features of AMD/Intel FPGA toolchains?
I was having a discussion with my colleagues, for us it’s the overcrowded UI. So many cluttered buttons and features, half of which we never use…
We were debating about what the most hated features would be in the wider FPGA community. Tell me your thoughts!
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